宁波大学数电实验参考答案 （仅供参考）
实验一 EDA工具软件的使用 异或门
F =
A B +A B
___
___
同或门
F =A B +AB
______
实验二 EDA开发平台使用 1、设计一个一位半加器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity banjia is port(
a,b : in std_logic; s,c: out std_logic ); end banjia;
architecture behav of banjia is begin s
2、二进制全加器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity fadder is port (
a :in std_logic; b :in std_logic;
c :in std_logic; s :out std_logic; d :out std_logic ); end fadder;
architecture behav of fadder is begin
s
d
实验五 MSI组合电路的HDL 设计 1、3—8译码器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity decoder38 is port (
x :in std_logic_vector(2 downto 0);
y :out std_logic_vector(7 downto 0) );
end decoder38;
architecture behav of decoder38 is begin process(x) begin case x is
when "000" => y y y y y y y y null; end case; end process; end behav;
2、显示译码器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity xianshi is port (
a :in std_logic_vector(3 downto 0); b :out std_logic_vector(6 downto 0) );
end xianshi;
architecture behav of xianshi is begin process(a) begin case a is
when "0000"=>bbbb
when "0100"=>bbbbbbbbbbbb null; end case; end process; end behav;
3、数据选择器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity select41 is port (
x :in std_logic_vector(1 downto 0); a :in std_logic; b :in std_logic; c :in std_logic; d :in std_logic; y :out std_logic );
end select41;
architecture behav of select41 is begin process(x) begin case x is
when "00" => y y y y null;
end case; end process; end behav;
实验六 用MSI 设计组合逻辑电路 1、输血血型验证
2、单“1”检测器
实验七 集成触发器及使用 1、用触发器设计四位异步计数器
2、用触发器设计四位移位寄存器
实验八 时序电路的HDL 设计 1、模可变计数器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity adder is port (
clk ); end adder; E G M y
:in std_logic;
--E='1'则使能 --G='1'为加,'0' 为减
:in std_logic; :in std_logic;
:in std_logic_vector(1 downto 0);--模选择 :out std_logic_vector(3 downto 0)--结果
architecture behav of adder is signal q begin
process(E,G,clk) begin if E='0' then
q'0');
elsif clk'event and clk='1' then
if G='1' then
if M="00" then
if q
q
:std_logic_vector(3 downto 0);
else q'0');
elsif M="01" then
if q
q
else q'0'); end if;
elsif M="10" then
if q
q
else q'0'); end if;
elsif M="11" then
q
end if;
elsif G='0' then if M="00" then
if q>"1110" then q
if q>"1000" then q
else q
end if;
elsif M="10" then
if q>"0110" then q
else q
end if;
end if;
end if; end process; y
2、移位寄存器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity shiftreg is port ( clk ); end shiftreg; clr load fx M y
:in std_logic;
:in std_logic; :in std_logic;
:in std_logic; --fx='1'则左移，'0' 右移 :in std_logic_vector(3 downto 0); :out std_logic_vector(3 downto 0)
architecture behav of shiftreg is signal q begin
:std_logic_vector(3 downto 0);
process(clk,clr,load) begin if clr='1' then
q'0');
elsif clk'event and clk='1' then
if load='1' then
q
elsif fx='1' then
q(3 downto 1)
elsif fx='0' then
q(2 downto 0)
end if;
end if;
end process; y
实验十 综合时序电路设计 1、序列发生器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity fangfa1 is port ( clk ); end fangfa1; y
:in std_logic;
:out std_logic_vector(7 downto 0)--结果
architecture behav of fangfa1 is signal q begin process(clk) begin
if clk'event and clk='1' then
q
:std_logic_vector(2 downto 0);
end if;
end process;
process(q) begin
case q is
when "000" =>yyyyyyyy
end process; end beha
或
2、序列检测器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity jiance2 is port ( clk ); end jiance2; din clr
:in std_logic;
--串行输入数据 --复位信号 --检测结果
:in std_logic; :in std_logic; :out std_logic
result
architecture behav of jiance2 is signal d
:std_logic_vector(3 downto 0);
signal y :std_logic_vector(3 downto 0); signal c :std_logic; begin d
process(clr,clk,din) --序列移位存储 begin
if clr='1' or c='1' then y
else if clk'event and clk='1' then y
process(clk,y) --比较序列 begin
if clk'event and clk='0' then --同步时钟，去除毛刺 if y=d then
result
c
else result
c
end if; else null;
end if; end process;
end behav;
实验十一 多功能数字中的设计 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen is port( clk
load sw_set
:in std_logic; :in std_logic;
:in std_logic_vector(2 downto 0); :in std_logic_vector(3 downto 0); :out std_logic_vector(2 downto 0);
gw_set
Qa co
:out std_logic;
:out std_logic_vector(3 downto 0)
Qb ); end;
architecture a of fen is signal tema
:std_logic_vector(2 downto 0);
signal temb :std_logic_vector(3 downto 0); :std_logic_vector(2 downto 0); :std_logic_vector(3 downto 0);
signal sw_setreg signal gw_setreg begin
process(clk,load) begin
if load='1' then tema
if tema="101" then
--若时间达59时，则清零
if temb>="1001" then
tema
else temb
elsif temb>="1001" then
tema
else temb
end if;
Qa
end process;
end a;
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hours is
port(
clk
load sw_set :in std_logic; :in std_logic;
:in std_logic_vector(1 downto 0); :in std_logic_vector(3 downto 0); :out std_logic_vector(1 downto 0); :out std_logic_vector(3 downto 0) gw_set Qa Qb
);
end;
architecture a of hours is
signal tema
signal temb :std_logic_vector(1 downto 0); :std_logic_vector(3 downto 0);
:std_logic_vector(1 downto 0);
:std_logic_vector(3 downto 0); signal sw_setreg signal gw_setreg
begin
process(clk,load)
begin
if load='1' then tema
elsif (clk'event and clk='1') then
if tema="10" then --若时间达23时，则清零
if temb>="0011" then
tema
temb
else temb
end if;
elsif temb>="1001" then
tema
temb
else temb
end if;
end if;
Qa
end process;
end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity miao is
port(
clk,load
sw_set
:in std_logic; :in std_logic_vector(2 downto 0); :in std_logic_vector(3 downto 0); :out std_logic_vector(2 downto 0); gw_set
Qa co :out std_logic; :out std_logic_vector(3 downto 0) Qb
);
end;
architecture a of miao is
signal tema
signal temb :std_logic_vector(2 downto 0); :std_logic_vector(3 downto 0);
:std_logic_vector(2 downto 0);
:std_logic_vector(3 downto 0); signal sw_setreg signal gw_setreg
begin
process(clk,load)
begin
if load='1' then tema'0');temb'0'); elsif (clk'event and clk='1') then
if tema="101" then --若时间达59，则清零 if temb>="1001" then tema="1001" then tema
end if;
Qa
end process;
end a;
实验十二 交通信号灯的设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic is
port( clk1k rst :in std_logic; -------时钟信号(1khz) -------紧急控制信号 :in std_logic; etime :out std_logic_vector(3 downto 0); sr,sg,sy:out std_logic; ------南北方向红黄绿灯信号
er,eg,ey:out std_logic ------东西方向红黄绿灯信号
);
end traffic;
architecture behav of traffic is
type states is
(sta0,sta1,sta2,sta3,sta4,sta5,sta6,sta7,sta8,sta9,sta10,sta11,sta12,sta13,sta14,sta15,sta16,sta17,sta18,sta19,sta20,sta21);
signal current_state,next_state
signal temp1,temp2,temp3
signal temp4,temp5 :states:=sta0; :std_logic_vector(7 downto 0); :std_logic_vector(9 downto 0);
--分别用于指signal flag1,flag2,flag3,flag4 :std_logic;
示绿灯亮、绿灯闪烁、黄灯闪烁、分频
signal etimereg
:std_logic_vector(3 downto 0); signal end1,end2,end3 signal clk
的1hz 时钟
begin
process(clk1k,rst)
begin
if rst='1' then
current_state
elsif clk1k'event and clk1k='1' then
current_state
end if;
end process;
process(current_state)
begin
case current_state is
---------------sta0为初始状态-----------------------
when sta0=>
er
eg
ey
sr
sg
sy
flag1
flag2
flag3
flag4
etime
--stiem
next_state
---------------sta1为状态1：东西路口的绿灯亮，南北路口的红灯亮，持续10秒-----------------------
when sta1=>
er
ey
next_state
else next_state
---------------sta2-sta6为状态2：东西路口的绿灯闪烁，南北路口的红灯亮-----------------------
when sta2=>
er
flag1
er
eg
er
etime
when sta6=>
er
---------------sta7-sta9为状态3：东西路口的黄灯闪烁，南北路口的红灯亮-----------------------
when sta7=>
eg
when sta8=>
er
flag4
when sta9=>
er
when sta10=>
er
ey
when sta11=>
er
--stiem
next_state
---------------东西路口红灯亮，同时南北路口的绿灯亮，南北方向开始通车----------------------
when sta12=>
er
next_state
else next_state
---------------sta2-sta6为状态2：南北路口的绿灯闪烁，东西路口的红灯亮-----------------------
when sta13=>
eg
when sta14=>
er
flag4
when sta15=>
er
when sta16=>
er
eg
ey
sr
sg
sy
flag2
flag4
etime
--stime
next_state
when sta17=>
er
eg
ey
sr
sg
sy
flag2
flag4
etime
--stime
if end2='1' then --绿灯灭
next_state
---------------sta7-sta9为状态3：东西路口的黄灯闪烁，南北路口的红灯亮-----------------------
when sta18=>
er
when sta19=>
er
ey
etime
er
ey
etime
if end3='1' then next_state
when sta21=>
er
eg
ey
sg
sy
flag3
flag4
etime
next_state
end process;
--
process(flag1,clk) begin
if flag1='0' then
temp1
elsif clk'event and clk='0' then
if temp1>="00001001" then end1
end if;
end process;
process(flag2,clk) begin
if flag2='0' then
end2
elsif clk'event and clk='0' then end2
end process;
process(flag3,clk) begin
if flag3='0' then
end3
elsif clk'event and clk='0' then end3
end if;
end process;
process(flag4,clk) begin
if flag4='0' then
etimereg
elsif clk'event and clk='1' then etimereg
end process;
process(clk1k)
begin
if clk1k'event and clk1k='1' then
clk'0'); else temp4
end process; end behav;
宁波大学数电实验参考答案 （仅供参考）
实验一 EDA工具软件的使用 异或门
F =
A B +A B
___
___
同或门
F =A B +AB
______
实验二 EDA开发平台使用 1、设计一个一位半加器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity banjia is port(
a,b : in std_logic; s,c: out std_logic ); end banjia;
architecture behav of banjia is begin s
2、二进制全加器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity fadder is port (
a :in std_logic; b :in std_logic;
c :in std_logic; s :out std_logic; d :out std_logic ); end fadder;
architecture behav of fadder is begin
s
d
实验五 MSI组合电路的HDL 设计 1、3—8译码器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity decoder38 is port (
x :in std_logic_vector(2 downto 0);
y :out std_logic_vector(7 downto 0) );
end decoder38;
architecture behav of decoder38 is begin process(x) begin case x is
when "000" => y y y y y y y y null; end case; end process; end behav;
2、显示译码器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity xianshi is port (
a :in std_logic_vector(3 downto 0); b :out std_logic_vector(6 downto 0) );
end xianshi;
architecture behav of xianshi is begin process(a) begin case a is
when "0000"=>bbbb
when "0100"=>bbbbbbbbbbbb null; end case; end process; end behav;
3、数据选择器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity select41 is port (
x :in std_logic_vector(1 downto 0); a :in std_logic; b :in std_logic; c :in std_logic; d :in std_logic; y :out std_logic );
end select41;
architecture behav of select41 is begin process(x) begin case x is
when "00" => y y y y null;
end case; end process; end behav;
实验六 用MSI 设计组合逻辑电路 1、输血血型验证
2、单“1”检测器
实验七 集成触发器及使用 1、用触发器设计四位异步计数器
2、用触发器设计四位移位寄存器
实验八 时序电路的HDL 设计 1、模可变计数器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity adder is port (
clk ); end adder; E G M y
:in std_logic;
--E='1'则使能 --G='1'为加,'0' 为减
:in std_logic; :in std_logic;
:in std_logic_vector(1 downto 0);--模选择 :out std_logic_vector(3 downto 0)--结果
architecture behav of adder is signal q begin
process(E,G,clk) begin if E='0' then
q'0');
elsif clk'event and clk='1' then
if G='1' then
if M="00" then
if q
q
:std_logic_vector(3 downto 0);
else q'0');
elsif M="01" then
if q
q
else q'0'); end if;
elsif M="10" then
if q
q
else q'0'); end if;
elsif M="11" then
q
end if;
elsif G='0' then if M="00" then
if q>"1110" then q
if q>"1000" then q
else q
end if;
elsif M="10" then
if q>"0110" then q
else q
end if;
end if;
end if; end process; y
2、移位寄存器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity shiftreg is port ( clk ); end shiftreg; clr load fx M y
:in std_logic;
:in std_logic; :in std_logic;
:in std_logic; --fx='1'则左移，'0' 右移 :in std_logic_vector(3 downto 0); :out std_logic_vector(3 downto 0)
architecture behav of shiftreg is signal q begin
:std_logic_vector(3 downto 0);
process(clk,clr,load) begin if clr='1' then
q'0');
elsif clk'event and clk='1' then
if load='1' then
q
elsif fx='1' then
q(3 downto 1)
elsif fx='0' then
q(2 downto 0)
end if;
end if;
end process; y
实验十 综合时序电路设计 1、序列发生器 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity fangfa1 is port ( clk ); end fangfa1; y
:in std_logic;
:out std_logic_vector(7 downto 0)--结果
architecture behav of fangfa1 is signal q begin process(clk) begin
if clk'event and clk='1' then
q
:std_logic_vector(2 downto 0);
end if;
end process;
process(q) begin
case q is
when "000" =>yyyyyyyy
end process; end beha
或
2、序列检测器
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity jiance2 is port ( clk ); end jiance2; din clr
:in std_logic;
--串行输入数据 --复位信号 --检测结果
:in std_logic; :in std_logic; :out std_logic
result
architecture behav of jiance2 is signal d
:std_logic_vector(3 downto 0);
signal y :std_logic_vector(3 downto 0); signal c :std_logic; begin d
process(clr,clk,din) --序列移位存储 begin
if clr='1' or c='1' then y
else if clk'event and clk='1' then y
process(clk,y) --比较序列 begin
if clk'event and clk='0' then --同步时钟，去除毛刺 if y=d then
result
c
else result
c
end if; else null;
end if; end process;
end behav;
实验十一 多功能数字中的设计 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen is port( clk
load sw_set
:in std_logic; :in std_logic;
:in std_logic_vector(2 downto 0); :in std_logic_vector(3 downto 0); :out std_logic_vector(2 downto 0);
gw_set
Qa co
:out std_logic;
:out std_logic_vector(3 downto 0)
Qb ); end;
architecture a of fen is signal tema
:std_logic_vector(2 downto 0);
signal temb :std_logic_vector(3 downto 0); :std_logic_vector(2 downto 0); :std_logic_vector(3 downto 0);
signal sw_setreg signal gw_setreg begin
process(clk,load) begin
if load='1' then tema
if tema="101" then
--若时间达59时，则清零
if temb>="1001" then
tema
else temb
elsif temb>="1001" then
tema
else temb
end if;
Qa
end process;
end a;
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hours is
port(
clk
load sw_set :in std_logic; :in std_logic;
:in std_logic_vector(1 downto 0); :in std_logic_vector(3 downto 0); :out std_logic_vector(1 downto 0); :out std_logic_vector(3 downto 0) gw_set Qa Qb
);
end;
architecture a of hours is
signal tema
signal temb :std_logic_vector(1 downto 0); :std_logic_vector(3 downto 0);
:std_logic_vector(1 downto 0);
:std_logic_vector(3 downto 0); signal sw_setreg signal gw_setreg
begin
process(clk,load)
begin
if load='1' then tema
elsif (clk'event and clk='1') then
if tema="10" then --若时间达23时，则清零
if temb>="0011" then
tema
temb
else temb
end if;
elsif temb>="1001" then
tema
temb
else temb
end if;
end if;
Qa
end process;
end a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity miao is
port(
clk,load
sw_set
:in std_logic; :in std_logic_vector(2 downto 0); :in std_logic_vector(3 downto 0); :out std_logic_vector(2 downto 0); gw_set
Qa co :out std_logic; :out std_logic_vector(3 downto 0) Qb
);
end;
architecture a of miao is
signal tema
signal temb :std_logic_vector(2 downto 0); :std_logic_vector(3 downto 0);
:std_logic_vector(2 downto 0);
:std_logic_vector(3 downto 0); signal sw_setreg signal gw_setreg
begin
process(clk,load)
begin
if load='1' then tema'0');temb'0'); elsif (clk'event and clk='1') then
if tema="101" then --若时间达59，则清零 if temb>="1001" then tema="1001" then tema
end if;
Qa
end process;
end a;
实验十二 交通信号灯的设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic is
port( clk1k rst :in std_logic; -------时钟信号(1khz) -------紧急控制信号 :in std_logic; etime :out std_logic_vector(3 downto 0); sr,sg,sy:out std_logic; ------南北方向红黄绿灯信号
er,eg,ey:out std_logic ------东西方向红黄绿灯信号
);
end traffic;
architecture behav of traffic is
type states is
(sta0,sta1,sta2,sta3,sta4,sta5,sta6,sta7,sta8,sta9,sta10,sta11,sta12,sta13,sta14,sta15,sta16,sta17,sta18,sta19,sta20,sta21);
signal current_state,next_state
signal temp1,temp2,temp3
signal temp4,temp5 :states:=sta0; :std_logic_vector(7 downto 0); :std_logic_vector(9 downto 0);
--分别用于指signal flag1,flag2,flag3,flag4 :std_logic;
示绿灯亮、绿灯闪烁、黄灯闪烁、分频
signal etimereg
:std_logic_vector(3 downto 0); signal end1,end2,end3 signal clk
的1hz 时钟
begin
process(clk1k,rst)
begin
if rst='1' then
current_state
elsif clk1k'event and clk1k='1' then
current_state
end if;
end process;
process(current_state)
begin
case current_state is
---------------sta0为初始状态-----------------------
when sta0=>
er
eg
ey
sr
sg
sy
flag1
flag2
flag3
flag4
etime
--stiem
next_state
---------------sta1为状态1：东西路口的绿灯亮，南北路口的红灯亮，持续10秒-----------------------
when sta1=>
er
ey
next_state
else next_state
---------------sta2-sta6为状态2：东西路口的绿灯闪烁，南北路口的红灯亮-----------------------
when sta2=>
er
flag1
er
eg
er
etime
when sta6=>
er
---------------sta7-sta9为状态3：东西路口的黄灯闪烁，南北路口的红灯亮-----------------------
when sta7=>
eg
when sta8=>
er
flag4
when sta9=>
er
when sta10=>
er
ey
when sta11=>
er
--stiem
next_state
---------------东西路口红灯亮，同时南北路口的绿灯亮，南北方向开始通车----------------------
when sta12=>
er
next_state
else next_state
---------------sta2-sta6为状态2：南北路口的绿灯闪烁，东西路口的红灯亮-----------------------
when sta13=>
eg
when sta14=>
er
flag4
when sta15=>
er
when sta16=>
er
eg
ey
sr
sg
sy
flag2
flag4
etime
--stime
next_state
when sta17=>
er
eg
ey
sr
sg
sy
flag2
flag4
etime
--stime
if end2='1' then --绿灯灭
next_state
---------------sta7-sta9为状态3：东西路口的黄灯闪烁，南北路口的红灯亮-----------------------
when sta18=>
er
when sta19=>
er
ey
etime
er
ey
etime
if end3='1' then next_state
when sta21=>
er
eg
ey
sg
sy
flag3
flag4
etime
next_state
end process;
--
process(flag1,clk) begin
if flag1='0' then
temp1
elsif clk'event and clk='0' then
if temp1>="00001001" then end1
end if;
end process;
process(flag2,clk) begin
if flag2='0' then
end2
elsif clk'event and clk='0' then end2
end process;
process(flag3,clk) begin
if flag3='0' then
end3
elsif clk'event and clk='0' then end3
end if;
end process;
process(flag4,clk) begin
if flag4='0' then
etimereg
elsif clk'event and clk='1' then etimereg
end process;
process(clk1k)
begin
if clk1k'event and clk1k='1' then
clk'0'); else temp4
end process; end behav;