[例5.6.1] 十进制计数器的VHDL 描述（sw 向上是0(on)；灯亮为0 ） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count10 is
PORT (cp,r:IN S TD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
end count10;
ARCHITECTURE Behavioral OF count10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGIN PROCESS (cp,r) BEGIN elsiF cp'EVENT AND cp='1' THEN if r='0' then count
if count="1001" THEN
count
ELSE count
END IF;
end if;
END PROCESS;
q
end Behavioral;
[例5.6.1] 十进制计数器的VHDL 描述（sw 向上是1；灯亮为1） library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count10 is
PORT (cp,r:IN S TD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
end count10;
ARCHITECTURE Behavioral OF count10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGIN PROCESS (cp,r) BEGIN elsiF cp'EVENT AND cp='1' THEN if r='1' then count
if count="1001" THEN
count
ELSE count
END IF;
end if;
END PROCESS;
q
end Behavioral;
[例5.6.1] 十进制计数器的VHDL 描述（sw 向上是0(on)；灯亮为0 ） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count10 is
PORT (cp,r:IN S TD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
end count10;
ARCHITECTURE Behavioral OF count10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGIN PROCESS (cp,r) BEGIN elsiF cp'EVENT AND cp='1' THEN if r='0' then count
if count="1001" THEN
count
ELSE count
END IF;
end if;
END PROCESS;
q
end Behavioral;
[例5.6.1] 十进制计数器的VHDL 描述（sw 向上是1；灯亮为1） library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count10 is
PORT (cp,r:IN S TD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
end count10;
ARCHITECTURE Behavioral OF count10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGIN PROCESS (cp,r) BEGIN elsiF cp'EVENT AND cp='1' THEN if r='1' then count
if count="1001" THEN
count
ELSE count
END IF;
end if;
END PROCESS;
q
end Behavioral;